A light emitting device 100 having the configuration shown in FIG. 32, for example, is known as a light emitting device (see JP 2010-199247 A).
The light emitting device 100 includes an LED chip 101 and a mounting substrate 102 on which the LED chip 101 is mounted.
The LED chip 101 includes, on one surface side of a translucent substrate 111, a laminated structure including an n-type nitride semiconductor layer 112, a nitride light emitting layer 113, and a p type nitride semiconductor layer 114. Regarding the LED chip 101, an anode electrode 107 is formed on an opposite side of the p-type nitride semiconductor layer 114 to the nitride light emitting layer 113. Further, regarding the LED chip 101, a cathode electrode 108 is formed on a side of the n-type nitride semiconductor layer 112 on which the nitride light emitting layer 113 is laminated.
Regarding the mounting substrate 102, conductive patterns 127, 128 are formed on one surface side of an insulating substrate 121. The anode electrode 107 of the LED chip 101 is joined to the conductive pattern 127 via a plurality of bumps 137. Further, the cathode electrode 108 of the LED chip 101 is joined to the conductive pattern 128 via a single bump 138.
An LED device (a semiconductor light emitting device) 210 having the configuration shown in FIG. 33, for example, is also known as a light emitting device (see JP 2011-204838 A).
The LED device 210 includes a circuit board 212 and an LED element 213 that is mounted on the circuit board 212 by flip-chip mounting.
A −electrode 214 (a first electrode) and a +electrode 215 (a second electrode) are formed on a plate material 216 of the circuit board 212.
The LED element 213 includes a sapphire substrate 225, an n-type semiconductor layer 221 (a first conductor layer), a light emitting layer (not shown), and a p-type semiconductor layer 222 (a second semiconductor layer). The LED element 213 also includes an n-side bump 223 (a first bump) connected to the n-type semiconductor layer 221, and a p-side bump 224 (a second bump) connected to the p-type semiconductor layer 222. The n-side bump 223 has a smaller surface area than the p-side bump 224. Each of the n-side bump 223 and the p-side bump 224 is constituted by an Au bump portion and a gold-tin eutectic layer. The n-side bump 223 and the p-side bump 224 each have a thickness between 10 and 15 μm. A thickness of the gold-tin eutectic layer is between 2 and 3 μm. A step of approximately 1 μm, which corresponds to a thickness of the p-type semiconductor layer 222, is provided between respective lower surfaces of the n-side bump 223 and the p-side bump 224.
The n-side bump 223 and the p-side bump 224 of the LED element 213 are connected respectively to the −electrode 214 and the +electrode 215 of the circuit board 212. A correction film 217 is formed on the −electrode 214 of the circuit board 212 in a connection region where the −electrode 214 is connected to the n-side bump 223. The correction film 217 is formed at a substantially equal thickness (approximately 1 μm) to the aforesaid step.
By providing the LED device 210 with the correction film 217, an amount of gold-tin alloy protruding from a connection region of the p-side bump 224 can be reduced. Further, in the LED device 210, there is no need to press down the p-side bump 224 excessively during a joining process for mounting the LED element 213 on the circuit board 212, and therefore an amount of pressure applied during the joining process can be reduced in comparison with a case where the correction film 217 is not provided.